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july 2003 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. am49lv128bm data sheet publication number 31022 revision a amendment 6 issue date june 17, 2004
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supplement publication number: 31022_00 rev: a amendment: 6 am49lv128bm stacked multi-chip package (mcp) 128 megabit (8 m x 16-bit) mirrorbit ? uniform sector flash memory and 32 mbit (2 m x 16-bit) pseudo-static ram with page mode distinctive characteristics architectural advantages ? single power supply operation ? 3 volt read, erase, and program operations ? manufactured on 0.23 m mirrorbit process technology ? secsi ? (secured silicon) sector region ? 128-word sector for permanent, secure identification through an 8-word random electronic serial number, accessible through a command sequence ? may be programmed and locked by the customer ? flexible sector architecture ? two hundred fifty-six 32 kword sectors ? compatibility with jedec standards ? provides pinout and software compatibility for single- power supply flash, and superior inadvertent write protection ? minimum 100,000 erase cycle guarantee per sector ? 20-year data retention at 125 c performance characteristics ? high performance ? as fast as 105 ns access time ? 25 ns page read times ? 0.5 s typical sector erase time ? 15 s typical write buffer word programming time: 16- word write buffer reduces overall programming time for multiple-word updates ? 4-word page read buffer ? 16-word write buffer ? low power consumption (typical values at 3.0 v, 5 mhz) ? 30 ma typical active read current ? 50 ma typical erase/program current ? 1 a typical standby mode current ? package option ?64-ball fbga software & hardware features ? software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? unlock bypass program command reduces overall multiple-word or byte programming time ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices ? hardware features ? sector group protection: hardware-level method of preventing write operations within a sector group ? temporary sector group unprotect: v id -level method of changing code in locked sector groups ? wp#/acc input accelerates programming time (when high voltage is applied) for greater throughput during system production. protects last sector regardless of sector protection settings ? hardware reset input (reset#) resets device psram features ? asynchronous sram interface ? fast access time ?t ce = t aa = 65 ns max ? low voltage operating condition ?v dd = 2.7 to + 3.1 v ? byte control by lb# and ub#
2 am49lv128bm june 17, 2004 general description the 128 mbit mirrorbit device is a 128 mbit, 3.0 volt single power supply flash memory devices organized as 8,388,608 words. the device has a 16-bit wide data bus. the device can be programmed either in the host system or in standard eprom programmers. an access time of 105 or 110 ns is available. each de- vice has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0 volt power supply for both read and write functions. in addition to a v cc input, a high-voltage accelerated program ( wp#/ acc) input provides shorter programming times through increased current. this feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. the device is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the device using standard microprocessor write timing. write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase oper- ation has begun, the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits to de- termine whether the operation is complete. to facilitate programming, an unlock bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector group to read or program any other sector group and then complete the erase operation. the program suspend/program resume feature en- ables the host system to pause a program operation in a given sector group to read any other sector group and then complete the program operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the host system to read boot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the secsi ? (secured silicon) sector provides a 128-word area for code or data that can be perma- nently protected. once this sector is protected, no fur- ther changes within the sector can occur. the write protect (wp# /acc ) feature protects the last sector by asserting a logic low on the wp# pin. amd mirrorbit flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is programmed using hot electron injection. related documents for a comprehensive information on mirrorbit prod- ucts, including migration information, data sheets, ap- plication notes, and software drivers, please see www.amd.com flash memory product informa- tion mirrorbit flash information technical docu- mentation. the following is a partial list of documents closely related to this product: mirrorbit? flash memory write buffer programming and page buffer read implementing a common layout for amd mirrorbit and intel strataflash memory devices migrating from single-byte to three-byte device ids
june 17, 2004 am49lv128bm 3 table of contents continuity of specifications . . . . . . . . . . . 3 continuity of ordering part numbers . . . . . 3 for more information . . . . . . . . . . . . . . . . 3 distinctive characteristics . . . . . . . . . . . . . . . . . . . . general description . . . . . . . . . . . . . . . . . . . . . . 2 related documents . . . . . . . . . . . . . . . . . . . . . . . . 2 product selector guide . . . . . . . . . . . . . . . . . . . . . .4 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . .4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . .5 special package handling instructions . . . . 5 look ahead pinout . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . 9 device bus operations . . . . . . . . . . . . . . . . . . . . . . 10 device bus operations . . . . . . . . . . . . . . . . . 10 requirements for reading array data . . . 10 writing commands/command sequences 11 standby mode ........................................................................ 11 automatic sleep mode . . . . . . . . . . . . . . 11 reset#: hardware reset pin . . . . . . . . . 12 output disable mode . . . . . . . . . . . . . . . 12 sector address table . . . . . . . . . . . . . . . . . . 12 secsi (secured silicon) sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . 17 secsi sector contents . . . . . . . . . . . . . . . . 18 sector group protection and unprotection............................. 19 sector group protection/unprotection address table . . . . . . . . . . . . . . . . . . . . . . 19 write protect (wp#) ................................................................ 20 temporary sector group unprotect . . . . . 20 temporary sector group unprotect operation 20 in-system sector grou p protect/unprotect algorithms . . . . . . . . . . . . . . . . . . . . . . . . 21 hardware data protection . . . . . . . . . . . 22 common flash memory interface (cfi). . . . . . . .22 command definitions . . . . . . . . . . . . . . . . . . . . . . .24 reading array data . . . . . . . . . . . . . . . . 24 reset command . . . . . . . . . . . . . . . . . . 25 autoselect command sequence . . . . . . . 25 enter secsi sector/exit secsi sector command sequence . . . . . . . . . . . . . . . 25 word program command sequence . . . . . 25 write buffer programming operation . . . . . . . 28 program operation . . . . . . . . . . . . . . . . . . . 29 program suspend/program resume command sequence . . . . . . . . . . . . . . . 29 program suspend/program resume . . . . . . . 30 chip erase command sequence . . . . . . . 30 sector erase command sequence . . . . . . 30 erase operation . . . . . . . . . . . . . . . . . . . . . 31 erase suspend/erase resume commands 31 command definitions .............................................................. 32 write operation status . . . . . . . . . . . . . . . . . . . . . 33 dq7: data# polling . . . . . . . . . . . . . . . . 33 data# polling algorithm . . . . . . . . . . . . . . . . 33 dq6: toggle bit i. . . . . . . . . . . . . . . . . . 33 toggle bit algorithm . . . . . . . . . . . . . . . . . . 34 dq2: toggle bit ii . . . . . . . . . . . . . . . . . 34 reading toggle bits dq6/dq2 . . . . . . . . 35 dq5: exceeded timing limits . . . . . . . . . 35 dq3: sector erase timer . . . . . . . . . . . . 35 dq1: write-to-buffer abort . . . . . . . . . . . 35 write operation status . . . . . . . . . . . . . . . . 36 absolute maximum ratings . . . . . . . . . . . . . . . . . 37 maximum negative overshoot waveform . . 37 maximum positive overshoot waveform . . . 37 flash dc characteristics . . . . . . . . . . . . . . . . . . . . 38 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 test setup . . . . . . . . . . . . . . . . . . . . . . . . 39 test specifications . . . . . . . . . . . . . . . . . . . 39 key to switching waveforms. . . . . . . . . . . . . . . . 39 input waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40 vcc power-up ........................................................................ 40 v cc power-up diagram . . . . . . . . . . . . . . . . 40 read operations timings . . . . . . . . . . . . . . . 41 page read timings . . . . . . . . . . . . . . . . . . . 42 hardware reset (reset#) .................................................... 43 reset timings . . . . . . . . . . . . . . . . . . . . . . 43 erase and program operatio ns .............................................. 44 program operation timings . . . . . . . . . . . . . 45 accelerated program timing diagram. . . . . . 45 chip/sector erase operation timings . . . . . . 46 data# polling timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . 47 toggle bit timings (during embedded algorithms). . . . . . . . . . . . . . . . . . . . . . . . 48 dq2 vs. dq6 . . . . . . . . . . . . . . . . . . . . . . . . 48 temporary sector unprotect .................................................. 49 temporary sector group unprotect timing diagram . . . . . . . . . . . . . . . . . . . . . 49 sector group protect and unprotect timing diagram . . . . . . . . . . . . . . . . . . . . . 50 alternate ce# controlled erase and program operations .............................................................................. 51 alternate ce# controlled write (erase/program) operation timings 5. . . . . . . . . . . . . . . . . . . . 2 latchup characteristics . . . . . . . . . . . . . . . . . . . . 52 erase and programming performance. . . . . . . . . 53 bga package capacitance. . . . . . . . . . . . . . . . . . 53 data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 function truth table . . . . . . . . . . . . . . . . . . . . . . . 55 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 recommended operating conditions . . . . . . . . . 57 psram dc characteristics . . . . . . . . . . . . . . . . . . 58 psram ac characteristics . . . . . . . . . . . . . . . . . . 59 read operation . . . . . . . . . . . . . . . . . . . 59 write operation . . . . . . . . . . . . . . . . . . 60 power down parameters . . . . . . . . . . . . 61 other timing parameters . . . . . . . . . . . . 61 ac test conditions . . . . . . . . . . . . . . . . . 62 ac measurement output load circuit . . . . . . 62 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . 63
4 am49lv128bm june 17, 2004 read timing #1 (basic timing) . . . . . . . . . . 63 read timing #2 (oe# and address access) . . 64 read timing #3 (lb#/ub# byte access) . . . . 65 read timing #4 (page access after ce1# control access) . . . . . . . . . . . . . . . . . . . . . 65 read timing #5 (random and page address access) . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 write timing #1 (basic timing) . . . . . . . . . . 67 write timing #2 (we# control) . . . . . . . . . . 67 write timing #3-1 (we#/lb#/ub# byte write control) . . . . . . . . . . . . . . . . . . . . . . . . . . 68 write timing #3-2 (we#/lb#/ub# byte write control) . . . . . . . . . . . . . . . . . . . . . . . . . . 69 write timing #3-3 (we#/lb#/ub# byte write control) . . . . . . . . . . . . . . . . . . . . . . . . . . 70 write timing #3-4 (we#/lb#/ub# byte write control) . . . . . . . . . . . . . . . . . . . . . . . . . . 70 read/write timing #1-1 (ce1# control) . . . 71 read/write timing #1-2 (ce1#/we#/oe# control) . . . . . . . . . . . . . . . . . . . . . . . . . . 71 read/write timing #2 (oe#, we# control) . 72 read/write timing #3 (oe#, we#, lb#, ub# control) . . . . . . . . . . . . . . . . . . . . . . . . . . 72 power-up timing #1 . . . . . . . . . . . . . . . . . 73 power-up timing #2 . . . . . . . . . . . . . . . . . 73 power-down entry and exit timing. . . . . . . . 74 standby entry timing after read or write . . . 74 am49lv128bm mcp with second psram supplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 psram block diagram . . . . . . . . . . . . . . . . . . . . . 76 absolute maximum ratings (note 1) . . . . . . . . . .76 operating characteristics (over specified temperature range) . . . . . . . . . . . . . . . . . . . . . . . 77 output load circuit . . . . . . . . . . . . . . . . . . . . . . . . 78 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 timing of read cycle (ce# = oe# = v il , we# = v ih ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 timing waveform of read cycle (we#=v ih ) . . . 81 timing waveform of page mode read cycle (we# = v ih ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 timing waveform of write cycle (we# control). . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 timing waveform of write cycle (ce# control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 timing waveform for successive we# write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 timing waveform of page mode write cycle. . 86 reduced memory size (rms) . . . . . . . . . 86 partial array refresh (par) . . . . . . . . . . . 86 deep sleep mode . . . . . . . . . . . . . . . . . . 87 variable address register . . . . . . . . . . . . . . . . . . 88 variable address register (var) update timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 deep sleep mode - entry/exit timings . . . . . . . . 90 address patterns for par (a3 = 0, a4 = 1) . . . . . . 91 address patterns for rms (a3 = 1, a4 = 1) . . . . . 92 low power icc characteristics for psram . . . . 93 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . 94 tld064?64-ball fine-pitch ball grid array ............................. 94 revision summary. . . . . . . . . . . . . . . . . . . . . . . . . 95
june 17, 2004 am49lv128bm 5 product selector guide notes: 1. see ?ac characteristics? for full specifications. mcp block diagram part number am49lv128bm speed/ voltage option full voltage range v cc = 2.7?3.1 v flash psram 15 11 15, 11 max. access time (ns) 105 110 65 max. ce# access time (ns) 105 110 65 max. page access time (t pacc )253020 max. oe# access time (ns) 25 30 20 v ss /v ssq v cc s/v ccq reset# we# ce#f oe# ce1#ps ry/by# lb#ps ub#ps w p#/acc ce2ps 32 m bit pseudo static ram 128 m bit flash memory dq15 to dq0 dq15 to dq0 dq15 to dq 0 a22 to a0 a22 to a0 a0 to a19 a20 to a0
6 am49lv128bm june 17, 2004 connection diagrams special package handling instructions special handling is required for flash memory products in molded packages (tsop and bga). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. g3 g4 g7 g8 f3 f4 f7 f8 e3 e4 e5 e6 e7 e8 d3 d4 d5 d6 d7 d8 c3 c4 c5 c6 c7 c8 b5 b6 nc nc a8 a11 we# wp/acc# lb# a7 a19 a12 ce2ps reset# ub# a6 a3 a9 a13 a20 ry/by# a18 a5 a2 a10 a14 a17 a4 a1 dq6 nc dq1 v ss a0 h3 h4 h5 h6 h7 h8 dq13 dq15 dq4 dq3 dq9 oe# ce#f a1 g2 f2 e2 d2 h2 nc l5 l6 k3 k4 k5 k6 k7 k8 j3 j4 j5 j6 j7 j8 dq12 dq7 vccps v cc f dq10 dq0 ce#1ps dq5 dq14 nc dq11 dq2 dq8 nc nc m1 nc j2 g9 f9 e9 d9 a15 a21 a22 a16 h9 vccf nc a10 j9 v ss m10 nc 64-ball fine-pitch (fbga) top view, balls facing down
june 17, 2004 am49lv128bm 7 look ahead pinout in order to provide customers with a migration path to higher densities, as well as the option to stack more die in a package, fasl has prepared a standard pi- nout that supports: ? nor flash and sram densities up to 4 gigabits ? nor flash and psram densities up to 4 gigabits ? nor flash and psram and data storage densities up to 4 gigabits. the signal locations of the resultant mcp device are shown above. note that for different densities, the ac- tual package outline may vary. however, any pinout in any mcp will be a subset of the pinout above. in some cases, there may be outrigger balls in loca- tions outside the grid shown above. in such cases, the user is recommended to treat these as rfu?s, and not connect them to any other signal. in case of any further inquiries about the above look- ahead pinout, please refer to the application note on this subject, or contact the appropriate amd or fujitsu sales office. d2 e2 f2 g2 h2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 c5 d5 e5 h5 j5 k5 c6 d6 e6 h6 j6 k6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 wp# a3 a2 a0 ce#f1 ce#1ps vssds a7 a6 a5 v ss oe# dq0 dq8 clk lb# ub#s a18 dq1 dq9 dq10 dq2 ce#f2 wp/acc rst#f dq3 v cc f dq11 vccds we# ce2s1 dq4 v cc ps nc rst#ds a8 a19 a9 dq6 dq13 dq12 dq5 clk#ds a11 a12 a14 nc dq15 dq7 dq14 ce#1ds a15 a22 a16 nc v ss pseudo sram on ly shared flash onl y k2 ce#1ps k9 ce#1ps l3 l4 l5 l6 l7 l8 dq8 dq2 dq11 nc dq5 dq14 l2 ce#1ps l9 ce#1ps m3 m4 m5 m6 m7 m8 dq8 dq2 dq11 nc dq5 dq14 m2 ce#1ps m9 ce#1ps n1 p1 nc nc n2 nc p2 nc n9 p9 nc nc n10 nc p10 nc f5 g5 f6 g6 ry/by# v cc f a20 v cc ps c9 ry/by#ds c2 adv# a9 b9 nc nc a10 nc b10 nc a1 b1 nc nc a2 nc b2 nc
8 am49lv128bm june 17, 2004 pin description a22?a21 = 2 address inputs (flash) a20?a0 = 21 address inputs (flash and psram) dq14?dq0 = 15 data inputs/outputs dq15 = dq15 (data input/output) ce#f = chip enable input (flash) ce1#ps, ce2ps=chip enable (psram) oe# = output enable input (flash) we# = write enable input (flash) wp#/acc = hardware write protect input/pro- gramming acceleration input (flash) reset#f = hardware reset pin input (flash) v cc f = flash 3.0 volt-only single power sup- ply (see product selector guide for speed options and voltage supply tolerances) v cc ps = psram power supply v ss = device ground nc = pin not connected internally ub#s = upper byte control (psram) lb#s = lower byte control (psram) ry/by# = ready/busy output logic symbol 23 16 dq15?dq0 a20?a0 ce1#ps oe# reset#f wp#/acc ub#s lb#s ce2ps we# ry/by# a22?21
june 17, 2004 am49lv128bm 9 ordering information the order number (valid combination) is formed by the following: valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations am49lv128 b m a h 10 n t tape and reel t=7 inches s = 13 inches temperature range n = light industrial (?25 c to +85 c) speed option see product selector guide and valid combinations wp# protection h = high sector protection l = low sector protection psram blank= standard supplier a = second supplier process technology m = 0.23 m mirrorbit psram device density b= 32 mbits amd device number/description am49lv128bm stacked multi-chip package (mcp) flash memory and psram am29lv128m 128 megabit (8 m x 16-bit) flash memory and 32 mbit (2 m x 16-bit) pseudo static ram
10 am49lv128bm june 17, 2004 device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are a22:a0. sector addresses are a22:a15 in both modes. 2. the sector group protect and sector group unprotect functions may also be implemented via programming equipment. see the ?sector group protection and unprotection? section. 3. if wp# = v il , the first or last sector remains protected. if wp# = v ih , the first or last sector will be protected or unprotected as determined by the method described in ?write protect (wp#)?. all sectors are unprotected when shipped from the factory (the secsi sector may be factory protected depending on version ordered.) 4. d in or d out as required by command sequence, data polling, or sector protect algorithm (see figure 2). requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the ac read-only operations table for timing spec- ifications and to figure 14 for the timing diagram. refer to the dc characteristics table for the active current specification on reading array data. operation ce# oe# we# reset# wp# acc addresses (note 2) dq0? dq7 dq8? dq15 read l l h h xx a in d out d out write (program/erase) l h l h (note 3) x a in (note 4) (note 4) accelerated program l h l h (note 3) v hh a in (note 4) (note 4) standby v cc 0.3 v xx v cc 0.3 v xh x high-z high-z output disable l h h h xx x high-z high-z reset x x x l xx x high-z high-z sector group protect (note 2) lhl v id hx sa, a6 =l, a3=l, a2=l, a1=h, a0=l (note 4) x sector group unprotect (note 2) lhl v id hx sa, a6=h, a3=l, a2=l, a1=h, a0=l (note 4) x temporary sector group unprotect xxx v id hx a in (note 4) (note 4)
june 17, 2004 am49lv128bm 11 page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read oper- ation. this mode provides faster read access speed for random locations within a page. the page size of the device is 4 words. the appropriate page is se- lected by the higher address bits a(max)?a2. address bits a1?a0 determine the specific word within a page. this is an asynchronous operation; the microproces- sor supplies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pacc . when ce# is deasserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode ac- cesses are obtained by keeping the ?read-page ad- dresses? constant and changing the ?intra-read page? addresses. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. the ?word program command sequence? section has de- tails on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 2 indicates the address space that each sector occupies. refer to the dc characteristics table for the active current specification for the write mode. the ac char- acteristics section contains timing specification tables and timing diagrams for write operations. write buffer write buffer programming allows the system write to a maximum of 16 words in one programming operation. this results in faster effective programming time than the standard programming algorithms. see ?write buffer? for more information. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is prima- rily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to nor- mal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated pro- gramming, or device damage may result. wp# has an internal pullup; when unconnected, wp# is at v ih . autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autose- lect command sequence sections for more informa- tion. standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v io 0.3 v, the device will be in the standby mode, but the standby current will be greater. the de- vice requires standard access time (t ce ) for read ac- cess when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. refer to the dc characteristics table for the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard ad- dress access timings provide new data when ad- dresses are changed. while in sleep mode, output data is latched and always available to the system. refer to the dc characteristics table for the automatic sleep mode current specification.
12 am49lv128bm june 17, 2004 reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/ write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to ac- cept another command sequence, to ensure data in- tegrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby cur- rent will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. refer to the ac characteristics tables for reset# pa- rameters and to figure 16 for the timing diagram. v cc power-up and power-down sequencing the device imposes no restrictions on v cc power-up or power-down sequencing. asserting reset# to vil is required during the entire v cc power sequence until the respective supplies reach their operating voltages. once v cc attains its operating voltage, de-assertion of reset# to v ih is permitted. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. table 2. sector address table sector a22?a15 sector size (kwords) 16-bit address range (in hexadecimal) sa0 00000000 32 000000?007fff sa1 00000001 32 008000?00ffff sa2 00000010 32 010000?017fff sa3 00000011 32 018000?01ffff sa4 00000100 32 020000?027fff sa5 00000101 32 028000?02ffff sa6 00000110 32 030000?037fff sa7 00000111 32 038000?03ffff sa8 00001000 32 040000?047fff sa9 00001001 32 048000?04ffff sa10 00001010 32 050000?057fff sa11 00001011 32 058000?05ffff sa12 00001100 32 060000?067fff sa13 00001101 32 068000?06ffff sa14 00001110 32 070000?077fff sa15 00001111 32 078000?07ffff sa16 00010000 32 080000?087fff sa17 00010001 32 088000?08ffff sa18 00010010 32 090000?097fff sa19 00010011 32 098000?09ffff sa20 00010100 32 0a0000?0a7fff sa21 00010101 32 0a8000?0affff sa22 00010110 32 0b0000?0b7fff sa23 00010111 32 0b8000?0bffff sa24 00011000 32 0c0000?0c7fff sa25 00011001 32 0c8000?0cffff sa26 00011010 32 0d0000?0d7fff sa27 00011011 32 0d8000?0dffff sa28 00011100 32 0e0000?0e7fff
june 17, 2004 am49lv128bm 13 sa29 00011101 32 0e8000?0effff sa30 00011110 32 0f0000?0f7fff sa31 00011111 32 0f8000?0fffff sa32 00100000 32 100000?107fff sa33 00100001 32 108000?10ffff sa34 00100010 32 110000?117fff sa35 00100011 32 118000?11ffff sa36 00100100 32 120000?127fff sa37 00100101 32 128000?12ffff sa38 00100110 32 130000?137fff sa39 00100111 32 138000?13ffff sa40 00101000 32 140000?147fff sa41 00101001 32 148000?14ffff sa42 00101010 32 150000?157fff sa43 00101011 32 158000?15ffff sa44 00101100 32 160000?167fff sa45 00101101 32 168000?16ffff sa46 00101110 32 170000?177fff sa47 00101111 32 178000?17ffff sa48 00110000 32 180000?187fff sa49 00110001 32 188000?18ffff sa50 00110010 32 190000?197fff sa51 00110011 32 198000?19ffff sa52 00110100 32 1a0000?1a7fff sa53 00110101 32 1a8000?1affff sa54 00110110 32 1b0000?1b7fff sa55 00110111 32 1b8000?1bffff sa56 00111000 32 1c0000?1c7fff sa57 00111001 32 1c8000?1cffff sa58 00111010 32 1d0000?1d7fff sa59 00111011 32 1d8000?1dffff sa60 00111100 32 1e0000?1e7fff sa61 00111101 32 1e8000?1effff sa62 00111110 32 1f0000?1f7fff sa63 00111111 32 1f8000?1fffff sa64 01000000 32 200000?207fff sa65 01000001 32 208000?20ffff sa66 01000010 32 210000?217fff sa67 01000011 32 218000?21ffff sa68 01000100 32 220000?227fff sa69 01000101 32 228000?22ffff sa70 01000110 32 230000?237fff sa71 01000111 32 238000?23ffff sa72 01001000 32 240000?247fff sa73 01001001 32 248000?24ffff sa74 01001010 32 250000?257fff sa75 01001011 32 258000?25ffff sa76 01001100 32 260000?267fff table 2. sector address table (continued) sector a22?a15 sector size (kwords) 16-bit address range (in hexadecimal)
14 am49lv128bm june 17, 2004 sa77 01001101 32 268000?26ffff sa78 01001110 32 270000?277fff sa79 01001111 32 278000?27ffff sa80 01010000 32 280000?287fff sa81 01010001 32 288000?28ffff sa82 01010010 32 290000?297fff sa83 01010011 32 298000?29ffff sa84 01010100 32 2a0000?2a7fff sa85 01010101 32 2a8000?2affff sa86 01010110 32 2b0000?2b7fff sa87 01010111 32 2b8000?2bffff sa88 01011000 32 2c0000?2c7fff sa89 01011001 32 2c8000?2cffff sa90 01011010 32 2d0000?2d7fff sa91 01011011 32 2d8000?2dffff sa92 01011100 32 2e0000?2e7fff sa93 01011101 32 2e8000?2effff sa94 01011110 32 2f0000?2f7fff sa95 01011111 32 2f8000?2fffff sa96 01100000 32 300000?307fff sa97 01100001 32 308000?30ffff sa98 01100010 32 310000?317fff sa99 01100011 32 318000?31ffff sa100 01100100 32 320000?327fff sa101 01100101 32 328000?32ffff sa102 01100110 32 330000?337fff sa103 01100111 32 338000?33ffff sa104 01101000 32 340000?347fff sa105 01101001 32 348000?34ffff sa106 01101010 32 350000?357fff sa107 01101011 32 358000?35ffff sa108 01101100 32 360000?367fff sa109 01101101 32 368000?36ffff sa110 01101110 32 370000?377fff sa111 01101111 32 378000?37ffff sa112 01110000 32 380000?387fff sa113 01110001 32 388000?38ffff sa114 01110010 32 390000?397fff sa115 01110011 32 398000?39ffff sa116 01110100 32 3a0000?3a7fff sa117 01110101 32 3a8000?3affff sa118 01110110 32 3b0000?3b7fff sa119 01110111 32 3b8000?3bffff sa120 01111000 32 3c0000?3c7fff sa121 01111001 32 3c8000?3cffff sa122 01111010 32 3d0000?3d7fff sa123 01111011 32 3d8000?3dffff sa124 01111100 32 3e0000?3e7fff table 2. sector address table (continued) sector a22?a15 sector size (kwords) 16-bit address range (in hexadecimal)
june 17, 2004 am49lv128bm 15 sa125 01111101 32 3e8000?3effff sa126 01111110 32 3f0000?3f7fff sa127 01111111 32 3f8000?3fffff sa128 10000000 32 400000?407fff sa129 10000001 32 408000?40ffff sa130 10000010 32 410000?417fff sa131 10000011 32 418000?41ffff sa132 10000100 32 420000?427fff sa133 10000101 32 428000?42ffff sa134 10000110 32 430000?437fff sa135 10000111 32 438000?43ffff sa136 10001000 32 440000?447fff sa137 10001001 32 448000?44ffff sa138 10001010 32 450000?457fff sa139 10001011 32 458000?45ffff sa140 10001100 32 460000?467fff sa141 10001101 32 468000?46ffff sa142 10001110 32 470000?477fff sa143 10001111 32 478000?47ffff sa144 10010000 32 480000?487fff sa145 10010001 32 488000?48ffff sa146 10010010 32 490000?497fff sa147 10010011 32 498000?49ffff sa148 10010100 32 4a0000?4a7fff sa149 10010101 32 4a8000?4affff sa150 10010110 32 4b0000?4b7fff sa151 10010111 32 4b8000?4bffff sa152 10011000 32 4c0000?4c7fff sa153 10011001 32 4c8000?4cffff sa154 10011010 32 4d0000?4d7fff sa155 10011011 32 4d8000?4dffff sa156 10011100 32 4e0000?4e7fff sa157 10011101 32 4e8000?4effff sa158 10011110 32 4f0000?4f7fff sa159 10011111 32 4f8000?4fffff sa160 10100000 32 500000?507fff sa161 10100001 32 508000?50ffff sa162 10100010 32 510000?517fff sa163 10100011 32 518000?51ffff sa164 10100100 32 520000?527fff sa165 10100101 32 528000?52ffff sa166 10100110 32 530000?537fff sa167 10100111 32 538000?53ffff sa168 10101000 32 540000?547fff sa169 10101001 32 548000?54ffff sa170 10101010 32 550000?557fff sa171 10101011 32 558000?55ffff sa172 10101100 32 560000?567fff table 2. sector address table (continued) sector a22?a15 sector size (kwords) 16-bit address range (in hexadecimal)
16 am49lv128bm june 17, 2004 sa173 10101101 32 568000?56ffff sa174 10101110 32 570000?577fff sa175 10101111 32 578000?57ffff sa176 10110000 32 580000?587fff sa177 10110001 32 588000?58ffff sa178 10110010 32 590000?597fff sa179 10110011 32 598000?59ffff sa180 10110100 32 5a0000?5a7fff sa181 10110101 32 5a8000?5affff sa182 10110110 32 5b0000?5b7fff sa183 10110111 32 5b8000?5bffff sa184 10111000 32 5c0000?5c7fff sa185 10111001 32 5c8000?5cffff sa186 10111010 32 5d0000?5d7fff sa187 10111011 32 5d8000?5dffff sa188 10111100 32 5e0000?5e7fff sa189 10111101 32 5e8000?5effff sa190 10111110 32 5f0000?5f7fff sa191 10111111 32 5f8000?5fffff sa192 11000000 32 600000?607fff sa193 11000001 32 608000?60ffff sa194 11000010 32 610000?617fff sa195 11000011 32 618000?61ffff sa196 11000100 32 620000?627fff sa197 11000101 32 628000?62ffff sa198 11000110 32 630000?637fff sa199 11000111 32 638000?63ffff sa200 11001000 32 640000?647fff sa201 11001001 32 648000?64ffff sa202 11001010 32 650000?657fff sa203 11001011 32 658000?65ffff sa204 11001100 32 660000?667fff sa205 11001101 32 668000?66ffff sa206 11001110 32 670000?677fff sa207 11001111 32 678000?67ffff sa208 11010000 32 680000?687fff sa209 11010001 32 688000?68ffff sa210 11010010 32 690000?697fff sa211 11010011 32 698000?69ffff sa212 11010100 32 6a0000?6a7fff sa213 11010101 32 6a8000?6affff sa214 11010110 32 6b0000?6b7fff sa215 11010111 32 6b8000?6bffff sa216 11011000 32 6c0000?6c7fff sa217 11011001 32 6c8000?6cffff sa218 11011010 32 6d0000?6d7fff sa219 11011011 32 6d8000?6dffff sa220 11011100 32 6e0000?6e7fff table 2. sector address table (continued) sector a22?a15 sector size (kwords) 16-bit address range (in hexadecimal)
june 17, 2004 am49lv128bm 17 secsi (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 256 bytes in length, and uses a secsi sector indicator bit (dq7) to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the secu- rity of the esn once the product is shipped to the field. amd offers the device with the secsi sector either customer lockable (standard shipping option) or fac- tory locked (contact an amd sales representative for ordering information). the customer-lockable version is shipped with the secsi sector unprotected, allowing customers to program the sector after receiving the device. the customer-lockable version also has the secsi sector indicator bit permanently set to a ?0.? the factory-locked version is always protected when shipped from the factory, and has the secsi (secured silicon) sector indicator bit permanently set to a ?1.? thus, the secsi sector indicator bit prevents cus- tomer-lockable devices from being used to replace de- vices that are factory locked. note that the acc sa221 11011101 32 6e8000?6effff sa222 11011110 32 6f0000?6f7fff sa223 11011111 32 6f8000?6fffff sa224 11100000 32 700000?707fff sa225 11100001 32 708000?70ffff sa226 11100010 32 710000?717fff sa227 11100011 32 718000?71ffff sa228 11100100 32 720000?727fff sa229 11100101 32 728000?72ffff sa230 11100110 32 730000?737fff sa231 11100111 32 738000?73ffff sa232 11101000 32 740000?747fff sa233 11101001 32 748000?74ffff sa234 11101010 32 750000?757fff sa235 11101011 32 758000?75ffff sa236 11101100 32 760000?767fff sa237 11101101 32 768000?76ffff sa238 11101110 32 770000?777fff sa239 11101111 32 778000?77ffff sa240 11110000 32 780000?787fff sa241 11110001 32 788000?78ffff sa242 11110010 32 790000?797fff sa243 11110011 32 798000?79ffff sa244 11110100 32 7a0000?7a7fff sa245 11110101 32 7a8000?7affff sa246 11110110 32 7b0000?7b7fff sa247 11110111 32 7b8000?7bffff sa248 11111000 32 7c0000?7c7fff sa249 11111001 32 7c8000?7cffff sa250 11111010 32 7d0000?7d7fff sa251 11111011 32 7d8000?7dffff sa252 11111100 32 7e0000?7e7fff sa253 11111101 32 7e8000?7effff sa254 11111110 32 7f0000?7f7fff sa255 11111111 32 7f8000?7fffff table 2. sector address table (continued) sector a22?a15 sector size (kwords) 16-bit address range (in hexadecimal)
18 am49lv128bm june 17, 2004 function and unlock bypass modes are not available when the secsi sector is enabled. the secsi sector address space in this device is allo- cated as follows: the system accesses the secsi sector through a command sequence (see ?enter secsi sector/exit secsi sector command sequence?). after the system has written the enter secsi sector command se- quence, it may read the secsi sector by using the ad- dresses normally occupied by the first sector (sa0). this mode of operation continues until the system is- sues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to sector sa0. customer lockable: secsi sector not programmed or protect ed at the factory unless otherwise specified, the device is shipped such that the customer may program and protect the 256- byte secsi sector. the system may program the secsi sector using the write-buffer, accelerated and/or unlock bypass meth- ods, in addition to the standard programming com- mand sequence. see command definitions. programming and protecting the secsi sector must be used with caution since, once protected, there is no procedure available for unprotecting the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. the secsi sector area can be protected using one of the following procedures: ? write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, ex- cept that reset# may be at either v ih or v id . this allows in-system protection of the secsi sector without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. ? to verify the protect/unprotect status of the secsi sector, follow the algorithm shown in figure 3. once the secsi sector is programmed, locked and verified, the system must write the exit secsi sector region command sequence to return to reading and writing within the remainder of the array. factory locked: secsi s ector programmed and protected at the factory in devices with an esn, the secsi sector is protected when the device is shipped from the factory. the secsi sector cannot be modified in any way. an esn factory locked device has an 16-byte random esn at ad- dresses 000000h?000007h. please contact your local amd sales representative for details on ordering esn factory locked devices. customers may opt to have their code programmed by amd through the amd expressflash service (express flash factory locked). the devices are then shipped from amd?s factory with the secsi sector permanently locked. contact an amd representative for details on using amd?s expressflash service. note: mcp devices with second supplier psram have 000000h address programmed to 0000h data. table 3. secsi sector contents secsi sector address range customer lockable esn factory locked expressflash factory locked 000000h?000007h determined by customer esn esn or determined by customer 000008h?00007fh unavailable determined by customer
june 17, 2004 am49lv128bm 19 sector group protection and unprotection the hardware sector group protection feature disables both program and erase operations in any sector group. the hardware sector group unprotection fea- ture re-enables both program and erase operations in previously protected sector groups. sector group pro- tection/unprotection can be implemented via two methods. sector group protection/unprotection requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algorithms and figure 24 shows the timing diagram. this method uses standard microprocessor bus cycle timing. for sector group unprotect, all unpro- tected sector group must first be protected prior to the first sector group unprotect write cycle. the device is shipped with all sector groups unpro- tected. amd offers the option of programming and protecting sector groups at its factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector group is protected or unprotected. see the sector group pro- tection and unprotection section for details. table 4. sector group protection/unprotection address table sector group a22?a15 sa0 00000000 sa1 00000001 sa2 00000010 sa3 00000011 sa4?sa7 000001xx sa8?sa11 000010xx sa12?sa15 000011xx sa16?sa19 000100xx sa20?sa23 000101xx sa24?sa27 000110xx sa28?sa31 000111xx sa32?sa35 001000xx sa36?sa39 001001xx sa40?sa43 001010xx sa44?sa47 001011xx sa48?sa51 001100xx sa52?sa55 001101xx sa56?sa59 001110xx sa60?sa63 001111xx sa64?sa67 010000xx sa68?sa71 010001xx sa72?sa75 010010xx sa76?sa79 010011xx sa80?sa83 010100xx sa84?sa87 010101xx sa88?sa91 010110xx sa92?sa95 010111xx sa96?sa99 011000xx sa100?sa103 011001xx sa104?sa107 011010xx sa108?sa111 011011xx sa112?sa115 011100xx sa116?sa119 011101xx sa120?sa123 0 11110xx sa124?sa127 0 11111xx sa128?sa131 100000xx sa132?sa135 100001xx sa136?sa139 100010xx sa140?sa143 100011xx sa144?sa147 100100xx sa148?sa151 100101xx sa152?sa155 100110xx sa156?sa159 100111xx sa160?sa163 101000xx sa164?sa167 101001xx sa168?sa171 101010xx sa172?sa175 101011xx sa176?sa179 101100xx sa180?sa183 101101xx sa184?sa187 101110xx sa188?sa191 10 1111xx sa192?sa195 110000xx sa196?sa199 110001xx sa200?sa203 110010xx sa204?sa207 110011xx sa208?sa211 110100xx sa212?sa215 110101xx sa216?sa219 110110xx sa220?sa223 110111xx sa224?sa227 111000xx sa228?sa231 111001xx sa232?sa235 111010xx sa236?sa239 111011xx sa240?sa243 111100xx sa244?sa247 111101xx sa248?sa251 111110xx sa252 11111100 sa253 11111101 sa254 11111110 sa255 11111111 sector group a22?a15
20 am49lv128bm june 17, 2004 write protect (wp#) the write protect function provides a hardware method of protecting the last sector without using v id . write protect is one of two functions provided by the wp#/acc input. if the system asserts v il on the wp#/acc pin, the de- vice disables program and erase functions in the last sector independently of whether those sectors were protected or unprotected using the method described in ?sector group protection and unprotection?. note that if wp#/acc is at v il when the device is in the standby mode, the maximum input load current is in- creased. see the table in ?dc characteristics?. if the system asserts v ih on the wp#/acc pin, the de- vice reverts to whether the last sector was previously set to be protected or unprotected using the method described in ?sector group protection and unprotec- tion?. note that wp# has an internal pullup; when un- connected, wp# is at v ih . temporary sector group unprotect this feature allows temporary unprotection of previ- ously protected sector groups to change data in-sys- tem. the sector group unprotect mode is activated by setting the reset# pin to vid. during this mode, for- merly protected sector groups can be programmed or erased by selecting the sector group addresses. once v id is removed from the reset# pin, all the previ- ously protected sector groups are protected again. figure 1 shows the algorithm, and figure 23 shows the timing diagrams, for this feature. figure 1. temporary sector group unprotect operation start perform erase or program operations reset# = v ih temporary sector group unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sector groups unprotected (if wp# = v il , the last sector group will remain protected). 2. all previously protected sector groups are protected once again.
june 17, 2004 am49lv128bm 21 figure 2. in-system sector group protect/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 ? verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary secto r unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no s ector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
22 am49lv128bm june 17, 2004 hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 9 for com- mand definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the sys- tem writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 5?8. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 5?8. the system must write the reset command to return the de- vice to reading array data. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. al- ternatively, contact an amd representative for copies of these documents. table 5. cfi query identification string addresses (x16) data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists)
june 17, 2004 am49lv128bm 23 table 6. system interface string table 7. device geometry definition addresses (x16) data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0007h typical timeout per single byte/word write 2 n s 20h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0001h max. timeout for byte/word write 2 n times typical 24h 0005h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) addresses (x16) data description 27h 0018h device size = 2 n byte 28h 29h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0001h number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 00ffh 0000h 0000h 0001h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 0000h 0000h 0000h 0000h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100)
24 am49lv128bm june 17, 2004 table 8. primary vendor-specific extended query command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. table 9 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase- addresses (x16) data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0008h address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0010b = 0.23 m mirrorbit 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0004h sector protect/unprotect scheme 04 = 29lv800 mode 4ah 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0001h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0004h/ 0005h top/bottom boot sector flag 00h = uniform device without wp# protect, 02h = bottom boot device, 03h = top boot device, 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h 0001h program suspend 00h = not supported, 01h = supported
june 17, 2004 am49lv128bm 25 suspended sector. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same excep- tion. see the erase suspend/erase resume com- mands section for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the device is in the autoselect mode. see the next section, reset command, for more infor- mation. see also requirements for reading array data in the device bus operations section for more information. the read-only operations table provides the read pa- rameters, and figure 14 shows the timing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming be- gins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the de- vice entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a write buffer pro- gramming operation, the system must write the write- to-buffer-abort reset command sequence to reset the device for the next operation. autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. tables 9 show the address and data requirements. the autoselect command sequence may be written to an address that is either in the read or erase-suspend- read mode. the autoselect command may not be writ- ten while the device is actively programming or eras- ing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence: ? a read cycle at address xx00h returns the manu- facturer code. ? three read cycles at addresses 01h, 0eh, and 0fh return the device code. ? a read cycle to an address containing a sector ad- dress (sa), and the address 02h on a7?a0 in word mode returns 01h if the sector is protected, or 00h if it is unprotected. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in erase suspend). enter secsi sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing an 8-word random electronic serial num- ber (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. the exit secsi sector command sequence returns the de- vice to normal operation. tables 9 show the address and data requirements for both command sequences. see also ?secsi (secured silicon) sector flash memory region? for further information. note that the acc function and unlock bypass modes are not avail- able when the secsi sector is enabled. word program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. tables 9 show the address and data requirements for the word program com- mand sequence.
26 am49lv128bm june 17, 2004 when the embedded program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7 or dq6. refer to the write operation status sec- tion for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. note that the secsi sector, autoselect, and cfi functions are unavailable when a program opera- tion is in progress. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass pro- gram command, a0h; the second cycle contains the program address and data. additional data is pro- grammed in the same manner. this mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. tables 9 show the require- ments for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 90h. the second cycle must contain the data 00h. the device then returns to the read mode. write buffer programming write buffer programming allows the system write to a maximum of 16 words in one programming operation. this results in faster effective programming time than the standard programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load com- mand written at the sector address in which program- ming will occur. the fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. for example, if the system will pro- gram 6 unique address locations, then 05h should be written to the device. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the program buffer to flash command. the number of locations to program cannot exceed the size of the write buffer or the operation will abort. the fifth cycle writes the first address location and data to be programmed. the write-buffer-page is se- lected by address bits a max ?a 4 . all subsequent ad- dress/data pairs must fall within the selected-write- buffer-page. the system then writes the remaining ad- dress/data pairs into the write buffer. write buffer loca- tions may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be per- formed across multiple write-buffer pages. this also means that write buffer programming cannot be per- formed across multiple sectors. if the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. note that if a write buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. the host system must therefore account for loading a write- buffer location more than once. the counter decre- ments for each data load operation, not for each unique write-buffer-address location. note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. once the specified number of write buffer locations have been loaded, the system must then write the pro- gram buffer to flash command at the sector address. any other address and data combination aborts the write buffer programming operation. the device then begins programming. data polling should be used while monitoring the last address location loaded into the write buffer. dq7, dq6, dq5, and dq1 should be monitored to determine the device status during write buffer programming. the write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command. the write buffer programming sequence can be aborted in the following ways:
june 17, 2004 am49lv128bm 27 ? load a value that is greater than the page buffer size during the number of locations to program step. ? write to an address in a sector different than the one specified during the write-buffer-load com- mand. ? write an address/data pair to a different write- buffer-page than the one selected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded), dq6 = toggle, and dq5=0. a write-to-buffer-abort reset command sequence must be written to reset the de- vice for the next operation. note that the full 3-cycle write-to-buffer-abort reset command sequence is re- quired when using write-buffer-programming features in unlock bypass mode. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? accelerated program the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program com- mand sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/ acc pin must not be at v hh for opera- tions other than accelerated programming, or device damage may result. wp# has an internal pullup; when unconnected, wp# is at v ih . figure 5 illustrates the algorithm for the program oper- ation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 17 for timing diagrams.
28 am49lv128bm june 17, 2004 figure 3. write buffer programming operation write ?write to buffer? command and sector address write number of addresses to program minus 1(wc) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pass read dq7 - dq0 at last loaded address read dq7 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= ?1?, then the device failed. if this flowchart location was reached because dq1= ?1?, then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1=1, write the write-buffer-programming-abort-reset command. if dq5=1, write the reset command. 4. see tables 9 and 10 for command sequences required for write buffer programming. (note 3) (note 1) (note 2)
june 17, 2004 am49lv128bm 29 figure 4. program operation program suspend/program resume command sequence the program suspend command allows the system to interrupt a programming operation or a write to buffer programming operation so that data can be read from any non-suspended sector. within the suspended sec- tor, data may be read from addresses outside of the page (for example, amax?a4) being programmed. when the program suspend command is written dur- ing a programming process, the device halts the pro- gram operation within 15 s maximum (5 s typical) and updates the status bits. addresses are not re- quired when writing the program suspend command. after the programming operation has been sus- pended, the system can read array data from any non- suspended sector or from selected addresses within the suspended sector (see previous paragraph). the program suspend command may also be issued dur- ing a programming operation while an erase is sus- pended. in this case, data may be read from any sectors not in erase suspend or program suspend. if a read is needed from the secsi sector area (one- time program area), then the user must use the proper command sequences to enter and exit this region. the system may also write the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autose- lect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. after the program resume command is written, the device reverts to programming. the system can deter- mine the status of the program operation using the dq7 or dq6 status bits, just as in the standard pro- gram operation. see write operation status for more information. the system must write the program resume com- mand (address bits are don?t care) to exit the program suspend mode and continue the programming opera- tion. further writes of the resume command are ig- nored. another program suspend command can be written after the device has resume programming. there is no time-out limit for the program suspend command. after the program suspend command is written, the device will stay in program suspend mode until the program resume command or the reset command/operation is written. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see tables 9 and 10 for program command sequence. program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- or program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 ?
30 am49lv128bm june 17, 2004 figure 5. program suspend/program resume chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 9 show the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to the write operation status section for infor- mation on these status bits. any commands written during the chip erase operation are ignored. note that the secsi sector, autoselect, and cfi functions are unavailable when an erase op- eration is in progress. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 6 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 19 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 10 shows the ad- dress and data requirements for the sector erase com- mand sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time- out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase com- mand is written. any command other than sector erase or erase suspend during the time-out pe- riod resets the device to the read mode. note that the secsi sector, autoselect, and cfi functions are unavailable when an erase operation is in progress. the system must rewrite the command sequence and any additional addresses and commands. the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7, dq6, or dq2 in the erasing sector. refer to the write opera- tion status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 6 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 19 section for timing diagrams.
june 17, 2004 am49lv128bm 31 erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written dur- ing the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a typi- cal of 5 s (maximum of 20 s) to suspend the erase operation. however, when the erase suspend com- mand is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the device enters the erase-suspend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device ?erase sus- pends? all sectors selected for erasure.) reading at any address within erase-suspended sectors pro- duces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for infor- mation on these status bits. after an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. the address of the erase-suspended sector is required when writ- ing this command. further writes of the resume com- mand are ignored. another erase suspend command can be written after the chip has resumed erasing. there is no time-out limit for the erase suspend com- mand. after the erase suspend command is written, the device will stay in erase suspend mode until the erase resume command or the reset command/op- eration is written. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress figure 6. erase operation notes: 1. see tables 9 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
32 am49lv128bm june 17, 2004 command definitions table 9. command definitions legend: x = don?t care ra = read address of the memory location to be read. rd = read data read from location ra during read operation. pa = program address. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a22?a15 uniquely select any sector. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t care in command sequences, except for rd, pd, and wc. 5. unless otherwise noted, address bits a22?a11 are don?t cares. 6. no unlock or command cycles required when device is in read mode. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when the device is in the autoselect mode, or if dq5 goes high while the device is providing status information. 8. the fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. see the autoselect command sequence section for more information. 9. the device id must be read in three cycles. 10. if wp# protects the highest address sector, the data is 98h for factory locked and 18h for not factory locked. if wp# protects the lowest address sector, the data is 88h for factory locked and 08h for not factory locked. 11. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 21. 12. the data is 00h for an unprotected sector and 01h for a protected sector. 13. command sequence resets device for next command after aborted write-to-buffer operation. 14. the unlock bypass command is required prior to the unlock bypass program command. 15. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 16. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 17. the erase resume command is valid only during the erase suspend mode. 18. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id (note 9) 4 555 aa 2aa 55 555 90 x01 227e x0e 2212 x0f 2200 secsi ? sector factory protect (note 10) 4 555 aa 2aa 55 555 90 x03 (note 10) sector group protect verify (note 12) 4 555 aa 2aa 55 555 90 (sa)x02 00/01 enter secsi sector region 3 555 aa 2aa 55 555 88 exit secsi sector region 4 555 aa 2aa 55 555 90 xxx 00 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer (note 11) 3 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (note 13) 3 555 aa 2aa 55 555 f0 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 14) 2 xxx a0 pa pd unlock bypass reset (note 15) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (note 16) 1 ba b0 program/erase resume (note 17) 1 ba 30 cfi query (note 18) 1 55 98
june 17, 2004 am49lv128bm 33 write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 10 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device out- puts on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is ac- tive for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the sys- tem reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 will appear on suc- cessive read cycles. table 10 shows the outputs for data# polling on dq7. figure 8 shows the data# polling algorithm. figure 20 in the ac characteristics section shows the data# polling timing diagram. figure 7. data# polling algorithm dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device has entered the erase dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?q0 addr = va read dq7?q0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
34 am49lv128bm june 17, 2004 suspend mode. toggle bit i may be read at any ad- dress, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approxi- mately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the de- vice enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alterna- tively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 10 shows the outputs for toggle bit i on dq6. figure 9 shows the toggle bit algorithm. figure 21 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 22 shows the differences be- tween dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii. figure 8. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce# to con- trol the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 10 to compare out- puts for dq2 and dq6. figure 9 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. figure 21 shows the toggle bit timing dia- gram. figure 22 shows the differences between dq2 and dq6 in graphical form. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
june 17, 2004 am49lv128bm 35 reading toggle bits dq6/dq2 refer to figure 9 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 9). dq5: exceeded timing limits dq5 indicates whether the program, erase, or write- to-buffer time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? in- dicating that the program or erase cycle was not success- fully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? in all these cases, the system must write the reset command (or the unlock bypass reset command if in unlock bypass mode) to return the device to the read- ing the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between addi- tional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 10 shows the status of dq3 relative to the other status bits. dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the write-to-buffer-abort- reset command sequence to return the device to reading array data. see write buffer programming section for more details.
36 am49lv128bm june 17, 2004 table 10. write operation status notes: 1. dq5 switches to ?1? when an embedded program, embedded erase, or write-to-buffer operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. dq1 switches to ?1? when the device has aborted the write-to-buffer operation. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle n/a program suspend mode program- suspend read program-suspended sector invalid (not allowed) non-program suspended sector data erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a non-erase suspended sector data erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a write-to- buffer busy (note 3) dq7# toggle 0 n/a n/a 0 abort (note 4) dq7# toggle 0 n/a n/a 1
june 17, 2004 am49lv128bm 37 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . ?65 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v v io . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +4.0 v a9 , oe#, acc, and reset# (note 2) . . . . . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins (note 1) . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 10. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 11. 2. minimum dc input voltage on pins a9, oe#, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 10. maximum dc input voltage on pin a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges light industrial (n) devices ambient temperature (t a ) . . . . . . . . . ?25c to +85c supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7?3.1 v note: operating ranges define those limits between which the functionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v figure 9. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 10. maximum positive overshoot waveform
38 am49lv128bm june 17, 2004 flash dc characteristics cmos compatible notes: 1. on the wp#/acc pin only, the maximum input load current when wp# = v il is 5.0 a. 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. maximum i cc specifications are tested with v cc = v cc max. 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. 6. if v io < v cc , maximum v il for ce# and dq i/os is 0.3 v io . maximum v ih for these connections is v io + 0.3 v 7. v cc voltage requirements. 8. v io voltage requirements. 9. not 100% tested. parameter symbol parameter description (notes) test conditions min typ max uni t i li input load current (1) v in = v ss to v cc , v cc = v cc max 1.0 a i lit acc input load current v cc = v cc max 35 a i lr reset leakage current v cc = v cc max ; reset# = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (2, 3) ce# = v il, oe# = v ih 5 mhz 15 20 ma 1 mhz 15 20 i cc2 v cc initial page read current (2, 3) ce# = v il, oe# = v ih 30 50 ma i cc3 v cc intra-page read current (2, 3) ce# = v il, oe# = v ih 10 20 ma i cc4 v cc active write current (3, 4) ce# = v il, oe# = v ih 50 60 ma i cc5 v cc standby current (3) ce#, reset# = v cc 0.3 v, wp# = v ih 15a i cc6 v cc reset current (3) reset# = v ss 0.3 v, wp# = v ih 15a i cc7 automatic sleep mode (3, 5) v ih = v cc 0.3 v; v il = v ss 0.3 v, wp# = v ih 15a v il input low voltage 1(6, 7) ?0.5 0.8 v v ih input high voltage 1 (6, 7) 1.9 v cc + 0.5 v v hh voltage for acc program acceleration v cc = 2.7?3.1 v 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7?3.1 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min = v io 0.15 x v io v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min = v io 0.85 v io v v oh2 i oh = ?100 a, v cc = v cc min = v io v io ?0.4 v v lko low v cc lock-out voltage (7) 2.3 2.5 v
june 17, 2004 am49lv128bm 39 test conditions table 11. test specifications note: if v io < v cc , the reference level is 0.5 v io . key to switching waveforms 2.7 k ? c l 6.2 k ? 3.3 v device under te s t note: diodes are in3064 or equivalent figure 11. test setup test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels (see note) 1.5 v output timing measurement reference levels 0.5 v io v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 0.5 v io v output measurement level input note: if v io < v cc , the input measurement reference level is 0.5 v io . figure 12. input waveforms and measurement levels
40 am49lv128bm june 17, 2004 ac characteristics v cc power-up figure 13. v cc power-up diagram parameter description test setup speed unit t vcs v cc setup time min 50 s t rsth reset# low hold time min 50 s v cc r eset# t vcs t rsth
june 17, 2004 am49lv128bm 41 ac characteristics flash read-only operations notes: 1. not 100% tested. 2. see figure 12 and table 11 for test specifications. 3. ac specifications are tested with v io = v cc . contact amd for information on ac operations with v io v cc. figure 14. read operations timings parameter description test setup 15 11 jedec std. unit t avav t rc read cycle time (note 1) min 105 110 ns t avqv t acc address to output delay ce#, oe# = v il max 105 110 ns t elqv t ce chip enable to output delay oe# = v il max 105 110 ns t pacc page access time max 25 30 ns t glqv t oe output enable to output delay max 25 30 ns t ehqz t df chip enable to output bus release (note 1) max 14 ns t ghqz t df output enable to output bus release (note 1) max 14 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v ry/by# reset# t df t oh
42 am49lv128bm june 17, 2004 ac characteristics figure 15. page read timings a22 - a2 ce# oe# a1 - a0 data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
june 17, 2004 am49lv128bm 43 ac characteristics hardware reset (reset#) note: not 100% tested. parameter description unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s reset# t rp t ready reset timings not during embedded algorithms ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp figure 16. reset timings
44 am49lv128bm june 17, 2004 ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words. 4. effective write buffer specification is based upon a 16-word write buffer operation. parameter 15 11 jedec std. description unit t avav t wc write cycle time (note 1) min 105 110 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ 15 s accelerated effective write buffer program operation (notes 2, 4) per word typ 11.8 s program operation (note 2) word typ 60 s accelerated programming operation (note 2) word typ 54 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s
june 17, 2004 am49lv128bm 45 ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) t ch pa n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. 2 . illustration shows device in word mode. figure 17. program operation timings acc t vhh v hh v il or v ih v il or v ih t vhh figure 18. accelerated program timing diagram
46 am49lv128bm june 17, 2004 ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status?. 2. these waveforms are for the word mode. figure 19. chip/sector erase operation timings
june 17, 2004 am49lv128bm 47 ac characteristics we# ce# oe# high z t oe high z dq7 dq0?q6 complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 20. data# polling timings (during embedded algorithms)
48 am49lv128bm june 17, 2004 ac characteristics oe# ce# we# a ddresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid dat a valid status valid status valid status note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 21. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 22. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
june 17, 2004 am49lv128bm 49 ac characteristics temporary sector unprotect note: not 100% tested. parameter jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s r eset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# t vidr t rsp program or erase command sequence figure 23. temporary sector gr oup unprotect timing diagram
50 am49lv128bm june 17, 2004 ac characteristics sector group protect: 150 s, sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect or unprotect verify v id v ih * for sector group protect, a6 = 0, a1 = 1, a0 = 0. for sector group unprotect, a6 = 1, a1 = 1, a0 = 0. figure 24. sector group protect and unprotect timing diagram
june 17, 2004 am49lv128bm 51 ac characteristics alternate ce# controlled erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words. 4. effective write buffer specification is based upon a 16-word write buffer operation. parameter 15, 11 jedec std. description unit t avav t wc write cycle time (note 1) min 65 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ 15 s effective accelerated write buffer program operation (notes 2, 4) per word typ 11.8 s program operation (note 2) word typ 60 s accelerated programming operation (note 2) word typ 54 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec
52 am49lv128bm june 17, 2004 ac characteristics latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. figure 25. alternate ce# contro lled write (erase/program) operation timings
june 17, 2004 am49lv128bm 53 erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 100,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90 c, v cc = 3.0 v, 100,000 cycles. 3. effective write buffer specification is based upon a 16-word write buffer operation. 4. the typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 5. in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure. 6. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 10 for further information on command definitions. 7. the device has a minimum erase and program cycle endurance of 100,000 cycles. bga package capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 15 sec excludes 00h programming prior to erasure (note 5) chip erase time 128 sec effective write buffer program time (note 3) per word 15 1000 s excludes system level overhead (note 6) program time word 60 1000 s effective accelerated program time (note 3) word 11.8 785 s accelerated program time word 54 900 s chip program time (note 4) 126 sec parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 fbga 4.2 5 pf c out output capacitance v out = 0 fbga 5.4 6.5 pf c in2 control pin capacitance v in = 0 fbga 3.9 4.7 pf parameter description test conditions min unit minimum pattern data retention time 150 c10years 125 c20years
54 am49lv128bm june 17, 2004 am49lv128bm mcp with standard supplier psram block diagram a20 to a0 address latch & buffer row decoder memory cell array 33,554,432 bit column / decoder input data latch & control output data control d q16 to dq9 dq8 to dq1 address latch & buffer sense / switch v dd v ss we ub ce2 lb timing control input / output buffer ce1 power control oe
june 17, 2004 am49lv128bm 55 function truth table note: 1. should not be kept this logic condition longer than 1 s. 2. power down mode can be entered from standby state and all dq pins are in high-z state. data retention depends on the selection of power down program. refer to power down for details. 3. can be either v il or v ih but must be valid for read or write. 4. oe# can be vil during write operation if the following conditions are satisfied; write pulse is initiated by ce1# (refer to ce1# controlled write timing), or cycle time of the previous operation cycle is satisfied, oe stays during write cycle. mode ce2 ce1# we# oe# lb# ub# a20-0 dq7-0 dq15-8 standby (deselect) h h x x x x x high-z high-z output disable (note 1) hl h h h x (note 3) high-z high-z output disable (no read) hl h h valid high-z high-z read (upper byte) h l valid high-z output valid read (lower byte) l h valid output valid high-z read (word) l l valid output valid output valid no write l h (note 4) h h valid invalid invalid write (upper byte) h l valid invalid input valid write (lower byte) l h valid input valid invalid write (word) l l valid input valid input valid power down (note 2) l x x x x x high-z high-z
56 am49lv128bm june 17, 2004 power down power down the power down is to enter low power idle state when ce2 stays low. the psram has two power down modes, deep sleep and 8m partial. these can be pro- grammed by series of read/write operation. see the following table for mode features. the default state is sleep and it is the lowest power consumption but all data will be lost once ce2 is brought to low for power down. it is not required to program to sleep mode after power-up. power down program sequence the program requires total 6 read/write operation with unique address and data. between each read/write operation requires that device be in standby mode. the following table shows the detail sequence. the first cycle is to read from most significant address (msb). the second and third cycle are to write back the data (rda) read by first cycle. if the second or third cycle is written into the different address, the program is cancelled and the data written by the second or third cycle is valid as a normal write operation. the fourth and fifth cycle is to write to msb. the data of fourth and fifth cycle is don?t care. if the fourth or fifth cycle is written into different address, the program is also can- celled but write data may not be wrote as normal write operation. the last cycle is to read from specific ad- dress key for mode selection. once this program se- quence is performed from a partial mode, the write data may be lost. so, it should perform this program prior to regular read/write operation if partial mode is used. address key the address key has the following format. mode data retention retention address sleep (default) no n/a 8m partial 8m bit 00000h to 7ffffh cycle# operation address data 1st read 1fffffh (msb) read data (rda) 2nd write 1fffffh rda 3rd write 1fffffh rda 4th write 1fffffh don?t care (x) 5th write 1fffffh x 6th read address key read data (rdb) mode address a20 a19 a18-a0 binary sleep (default) 1 1 1 1fffffh 8m partial 1 0 1 17ffffh cycle# operation address data
june 17, 2004 am49lv128bm 57 recommended operating conditions notes: 1. maximum dc voltage on input and i/o pins are v dd + 0.2 v. during voltage transitions, inputs may positive overshoot to v dd + 1.0 v for periods of up to 5 ns. 2. minimum dc voltage on input or i/o pins are -0.3 v. during voltage transitions, inputs may negative overshoot v ss to -1.0 v for periods of up to 5 ns. parameter symbol min. max. unit supply voltage v dd 2.7 3.1 v v ss 00v high level input voltage v ih 0.8 v dd v dd + 0.2 and +3.6 v v ih 0.8 v dd v dd + 0.2 v low level input voltage v il -0.3 0.2 v dd v ambient temperature t a ?25 85 c
58 am49lv128bm june 17, 2004 psram dc characteristics notes: 1. all voltages are referenced to v ss . 2. dc characteristics are measured after following power-up timing. 3. i out depends on the output load conditions. parameter symbol test conditions min. max. unit input leakage current i li v in = v ss to v dd -1.0 +1.0 a output leakage current i lo v out = v ss to v dd , output disable -1.0 +1.0 a output high voltage level v oh v dd = v dd (min), i oh = ?0.5ma 2.4 ? v output low voltage level v ol i ol = 1 ma ? 0.4 v v dd power down current i ddps v dd = v dd max., v in = v ih or v il , ce2 0.2v sleep ? 10 a i ddp8 8m partial ? 50 a v dd standby current i dds v dd = v dd max., v in = v ih or v il , ce1# ? 1.5 ma i dds1 v dd = v dd max., v in 0.2 v or v in v dd ? 0.2 v, ce1# =ce2 vdd ? 0.2v ?80 a v dd active current i dda1 v dd = v dd max., v in = v ih or v il , ce1# = v il and ce2 = v ih , i out = 0 ma t rc /t wc = minimum ?30ma i dda2 t rc /t wc = 1 s? 3 ma v dd page read current i dda3 v dd = v dd max., v in = v ih or v il , ce1# = v il and ce2 = v ih , i out = 0 ma, t prc = min. ?10ma
june 17, 2004 am49lv128bm 59 psram ac characteristics read operation notes: 1. maximum value is applicable if ce1# is kept at low without change of address input of a3 to a20. 2. address should not be changed within minimum t rc. 3. the output load 50pf. 4. the output load 5pf. 5. applicable to a3 to a20 when ce1# is kept at low. 6. applicable only to a0, a1 and a2 when ce1# is kept at low for the page address access. 7. in case page read cycle is continued with keeping ce1# stays low, ce1# must be brought to high within 4 s. in other words, page read cycle must be closed within 4 s. 8. applicable when at least two of address inputs among applicable are switched from previous state. 9. t rc (min) and t prc (min) must be satisfied. parameter symbol value unit min. max. read cycle time (notes 1, 2) t rc 65 1000 ns ce1# access time (note 3) t ce ?65ns oe# access time (note 3) t oe ?40ns address access time (notes 3,5) t aa ?65ns lb#/ub# access time (note 3) t ba ?30ns page address access time (notes 3,6) t paa ?20ns page read cycle time (notes 1,6,7) t prc 25 1000 ns output data hold time (note 3) t oh 5?ns ce1# low to output low-z (note 4) t clz 5?ns oe# low to output low-z (note 4) t olz 0?ns lb#/ub# low to output high-z (note 4) t blz 0?ns ce1# high to output high-z (note 3) t chz ?20ns oe# high to output high-z (note 3) t ohz ?20ns lb#/ub# high to output high-z (note 3) t bhz ?20ns address setup time to ce1# low t asc -5 ? ns address setup time to oe# low t aso 10 ? ns address invalid time (notes 5,8) t ax ?ns address hold time from ce1# high (note 9) t chah -5 ? ns address hold time from oe# high t ohah -5 ? ns ce1# high pulse width t cp 12 ? ns
60 am49lv128bm june 17, 2004 psram ac characteristics write operation notes: 1. maximum value is applicable if ce1# is kept at low without any address change. 2. minimum value must be equal or greater than the sum of write pulse (t cw , t wp , t bw ) and write recovery time (t wcr , t wr or t br ). 3. write pulse is defined from high to low transition of ce1#, we#, or lb#/ub#, whichever occurs last. 4. applicable for byte mask only. byte mask setup time is defined to the high to low transition of ce1# or we# whichever occurs last. 5. applicable for byte mask only. byte mask hold time is defined from the low to high transition of ce1# or we# whichever occurs first. 6. write recovery is defined from low to high transition of ce1#, we#, or lb#/ub#, whichever occurs first. 7. if oe# is low after minimum t ohcl , read cycle is initiated. in other words, oe# must be brought to high within 5 ns after ce1# is brought to low. once read cycle is initiated, new write pulse should be input after minimum t rc is met 8. if oe# is low after new address input, read cycle is initiated. in other words, oe# must be brought to high at the same time or before new address valid. once read cycle is initiated, new write pulse should be input after minimum t rc is met and data bus is in high-z 9. absolute minimum values and defined at minimum v ih level. 10. if the actual value of t whol is shorter than the specified minimum values, the actual t aa of following read may become longer by the amount of subtracting the actual value from the specified minimum value. parameter symbol value unit min. max. write cycle time (notes 1, 2) t wc 65 1000 ns address setup time (note 3) t as 0?ns ce1# write pulse width (note 3) t cw 40 ? ns we# write pulse width (note 3) t wp 40 ? ns lb#/ub# write pulse width (note 3) t bw 40 ? ns lb#/ub# byte mask setup time (note 4) t bs -5 ? ns lb#/ub# byte mask hold time (note 5) t bh -5 ? ns ce1# write recovery time (note 6) t wrc 12 ? ns we# write recovery time (note 6) t wr 7.5 1000 ns lb#/ub# write recovery time (note 6) t br 12 1000 ns data setup time t ds 12 ? ns data hold time t dh 0?ns oe# high to ce1# low setup time for write (note 7) t ohcl -5 ? ns oe# high to address setup time for write (note 8) t oes 0?ns we#/ub#/lb# high to oe# low setup time for read (note 10) t whol 12 ? 10 lb# and ub# write pulse overlap t bwo 30 ? ns ce1# high pulse width t cp 12 ? ns address hold time for write end (note 3) t ah 0?ns
june 17, 2004 am49lv128bm 61 ac characteristics power down parameters notes: 1. applicable also to power up. 2. applicable when 8m partial mode is programmed. other timing parameters notes: 1. some data might be written into any address location if t chwx (min) is not satisfied 2. the input transition time (t t ) at ac testing is 5ns, as shown in ac test conditions below... if actual t t is longer than 5ns, it may violate ac specification of some timing parameters. parameter symbol value unit min. max. ce2 low setup time for power down entry t csp 10 ? ns ce2 low hold time after power down entry t c2lp 65 ? ns ce1# high hold time following ce2 high after power down exit (sleep mode only) (note 1) t chh 300 ? s ce1# high hold time following ce2 high after power down exit (not in sleep mode) (note 2) t chhp 1? s ce1# high setup time following ce2 high after power down exit (note 1) t chs 0?ns parameter symbol value unit min. max. ce#1 high to oe# invalid time for standby entry t chox 10 - ns ce#1 high to we# invalid time for standby entry (note 1) t chwx 10 - ns ce2 low hold time after power up t c2lh 50 ? s ce1# high hold time following ce2 high after power up t chh 300 ? s input transition time (note 2) t t 125ns
62 am49lv128bm june 17, 2004 ac characteristics ac test conditions figure 26. ac measurement output load circuit symbol description test setup 15, 11 unit v ih input high level v dd * 0.8 v v il input low level v dd * 0.2 v v ref input timing measurement level v dd * 0.5 v t t input transition time between v il and v ih 5ns device under test v dd v ss ou t 0.1 f 50pf
june 17, 2004 am49lv128bm 63 timing diagrams note: ce2 and we# must be high for entire read cycle. figure 27. read timing #1 (basic timing) t ce valid data output a ddress ce1# dq (output) oe# t chz t rc t clz t chah t cp address valid t asc t asc t ohz t oh t bhz lb / ub# t oe t ba t blz t olz
64 am49lv128bm june 17, 2004 note: ce2 and we# must be high for entire read cycle. figure 28. read timing #2 (oe# and address access) t aa valid data output a ddress ce1# dq (output) lb / ub# t ohz t oe t rc t olz address valid valid data output address valid t rc t oh t oh oe# t ax low t aa t ohah t aso
june 17, 2004 am49lv128bm 65 timing diagrams note: ce2 and we# must be high for entire read cycle. figure 29. read timing #3 (lb#/ub# byte access) note: ce2 and we# must be high for entire read cycle. figure 30. read timing #4 (page access after ce1# control access) t aa valid data output address ce1#,oe# dq0-dq7 (output) ub# t bhz t ba t rc t blz address valid valid data output t bhz t oh lb# t ax low t ba t ax dq8-dq15 (output) t blz t ba t blz t oh t bhz t oh valid data output valid data output (normal access) a ddress (a2-a0) ce 1# dq (output) oe# t chz t ce t rc t clz address valid valid data output (page access) address valid t prc t oh t oh t chah t asc t paa a ddress (a20-a3) address valid lb# / ub# t paa t oh t prc t paa t prc t oh address valid address valid t rc
66 am49lv128bm june 17, 2004 timing diagrams note: ce2 and we# must be high for entire read cycle. either or both lb# and ub# must be low when both ce1# and oe# are low. figure 31. read timing #5 (random and page address access) valid data output (normal access) a ddress (a2-a0) ce 1# dq (output) oe# t oe t rc t olz t blz t aa valid data output (page access) address valid t prc t oh t oh t rc t paa a ddress (a20-a3) address valid l b# / ub# t aa t oh address valid t rc t paa t prc t oh address valid address valid t rc t ax t ax t ba address valid low t aso
june 17, 2004 am49lv128bm 67 timing diagrams note: ce2 must be high for write cycle. figure 32. write timing #1 (basic timing) note: ce2 must be high for write cycle. figure 33. write timing #2 (we# control) t as valid data input address ce1# dq (input) we# t dh t ds t wc t ah t wp t cw lb #, ub# t bw address valid t as t br oe# t ohcl t as t as t wr t as t as t as address we# ce1# t wc t ah t wp lb#, ub# address valid t as t wr t wp valid data input dq (input) t dh t ds oe# t oes t ohz t wc valid data input t dh t ds low address valid t ohah t wr
68 am49lv128bm june 17, 2004 timing diagrams note: ce2 must be high for write cycle. figure 34. write timing #3-1 (we#/lb#/ub# byte write control) t as address we# ce1# t wc t wr t bw lb# address valid t as t wr t bw valid data input dq0-dq8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq8-dq15 (input) t bs t bh t bs t bh
june 17, 2004 am49lv128bm 69 note: ce2 must be high for write cycle. figure 35. write timing #3-2 (we#/lb#/ub# byte write control) t as address we# ce1# t wc t wr t bw lb# address valid t as t wr t bw valid data input dq0-dq7 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq8-dq15 (input) t bs t bh t bs t bh
70 am49lv128bm june 17, 2004 timing diagrams note: ce2 must be high for write cycle. figure 36. write timing #3-3 (we#/lb#/ub# byte write control) note: ce2 must be high for write cycle. figure 37. write timing #3-4 (we#/lb#/ub# byte write control) t as address we# ce1# t wc t br t bw lb# address valid t as t br t bw valid data input dq0-dq7 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq8-dq15 (input) t bs t bh t bs t bh t as address we# ce1# t wc t br t bw lb# address valid t as t br t bw dq0-dq7 (input) t dh t ds ub# t wc t dh t ds low address valid 8- dq dq15 (input) t dh t ds t as t br t bw t as t br t bw t dh t ds valid data input valid data input valid data input valid data input t bwo t bwo
june 17, 2004 am49lv128bm 71 timing diagrams note: write address is valid from either ce1# or we# of last falling edge. figure 38. read/write timing #1-1 (ce1# control) note: oe# can be fixed low during write operation if it is ce1# controlled write at read-write-read sequence. figure 39. read/write timing #1-2 (ce1#/we#/oe# control) read data output a ddress ce1# dq we# t wc t cw oe# t ohcl ub#,lb# t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wrc t chah t dh t clz t oh read data output a ddress ce1# dq we# t wc t wp oe# t ohcl u b#,lb# t oe t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t olz t oh read data output
72 am49lv128bm june 17, 2004 timing diagrams note: ce1# can be tied to low for we# and oe# controlled operation. figure 40. read/write timing #2 (oe#, we# control) note: ce#1 can be tied to low for we# and oe# controlled operation. figure 41. read/write timing #3 (oe#, we#, lb#, ub# control) read data output a ddress ce1# dq we# t wc t wp oe# u b#,lb# t oe write address t as t rc write data input t ds t ohz t oh t aa read address t wr t dh t olz t oh read data output t ohz low t aso t ohah t oes t ohah read data output a ddress ce1# dq we# t wc t bw oe# u b#,lb# t ba write address t as t rc write data input t ds t bhz t oh t aa read address t br t dh t blz t oh read data output t bhz low t aso t ohah t ohah t oes
june 17, 2004 am49lv128bm 73 timing diagrams note: the t c2lh specifies after v dd reaches specified minimum level. figure 42. power-up timing #1 note: the t chh specifies after v dd reaches specified minimum level and applicable to both ce1# and ce2. figure 43. power-up timing #2 t c2lh c e1# v dd v dd min 0v c e2 t chh t chs c e1# v dd v dd min 0v c e2 t chh
74 am49lv128bm june 17, 2004 timing diagrams note: this power down mode can be also used as a reset timing if power-up timing above could not be satisfied and power- down program was not performed prior to this reset. figure 44. power-down entry and exit timing note: both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period for standby mode from ce1# low to high transition. figure 45. standby entry timing after read or write t csp c e1# power down entry c e2 t c2lp t chh (t chhp ) power down mode power down exit t chs dq high-z t chox c e1# oe# we# active (read) standby active (write) standby t chwx
june 17, 2004 am49lv128bm 75 timing diagrams notes: 1. the all address inputs must be high from cycle #1 to #5. 2. after t cp following cycle #6, the power down program is completed and returned to the normal operation. a ddress ce1# dq* 3 we# t rc oe# l b#,ub# rda msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 key* 2 t wc t wc t wc t wc t rc t cp t cp t cp t cp t cp t cp * 3 cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 rda rda x x rdb
76 am49lv128bm june 17, 2004 am49lv128bm mcp with second psram supplier psram block diagram note: zz# = ce2ps on mcp pin-out. function truth table note: 1. when ub# and lb# are in select mode (low), i/o 0 - i/o 15 are affected as shown. when lb# only is in the select mode only i/o 0 - i/ o 7 are affected as shown. when ub# is in the select mode only i/o 8 - i/o 15 are affected as shown. 2. when the device is in standby mode, control inputs (we#, oe#, ub#, and lb#), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. when we# is invoked, the oe# input is internally disabled and has no effect on the circuit. absolute maximum ratings (note 1) note: 1. stresses greater than those listed above may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. mode ce# zz# we# oe# ub# lb# i/o 0 - i/o 15 (note1) power standby (note 2) h h x x x x high-z standby standby (note 2) x h x x h h high-z standby write l h l x (note 3) l (note 1) l (note 1) data in active read l h h l l (note 1) l (note 1) data out active active l h h h l l high-z active deep sleep x l x x x x high-z deep sleep item symbol rating unit voltage on any pin relative to v ss v in,out ?0.2 to v cc +0.3 v voltage on vcc supply relative to v ss v cc ?0.2 to 3.6 v power dissipation p d 1w storage temperature t stg ?40 to 125 o c operating temperature t a -25 to +85 o c
june 17, 2004 am49lv128bm 77 operating characteristics (over specified temperature range) note: 1. typical values are measured at vcc=vcc typ., ta=25c and not 100% tested. 2. this parameter is specified with the outputs disabled to avoid external loading effects. the user must add current required to drive output capacitance expected in the actual system. 3. this device assumes a standby mode if the chip is disabled (either ce# high or both ub# and lb# high). in order to achieve low standby current all inputs must be within 0.2v of either vcc or vss. item symbol test condition min typ (note 1) max unit supply voltage v cc 2.7 3.0 3.1 v supply voltage for i/o v ccq 2.7 3.0 v cc v input high voltage v ih 0.8v ccq v ccq +0.2 v input low voltage v il -0.2 0.2v ccq v output high voltage v oh i oh = 0.5ma 0.8v ccq v output low voltage v ol i ol = -0.5ma 0.2v ccq v input leakage current i li v in = 0 to v cc -1 1 a output leakage current i lo oe# = v ih or chip disabled -1 1 a read/write operating supply current @1 s cycle time (note 2) i cc1 v cc = 3.1v, v in =cmos levelschip enabled, i out = 0 3.0 ma read/write operating supply current @65 ns cycle time (note 2) i cc2 v cc = 3.1v, v in =cmos levels chip enabled, i out = 0 25.0 ma page mode operating supply current @65 ns cycle time (note 2) i cc2 v cc = 3.1v, v in =cmos levels chip enabled, i out = 0 25.0 ma maximum standby current (note 3) i sb1 v cc = 3.1v, v in =cmos levels chip disabled 80 1 20 a
78 am49lv128bm june 17, 2004 output load circuit
june 17, 2004 am49lv128bm 79 timing item symbol 65ns units min. max. read cycle time t rc 65 ns address access time t aa 65 ns page mode read cycle time t pc 25 20000 ns page mode access time t pa 25 ns chip enable to valid output t co 65 ns output enable to valid output t oe 20 ns byte select to valid output t lb , t ub 65 ns chip enable to low-z output t lz 10 ns output enable to low-z output t olz 5ns byte select to low-z output t lbz , t ubz 10 ns chip disable to high-z output t hz 05 ns output disable to high-z output t ohz 05 ns byte select disable to high-z output t lbhz , t ubhz 05 ns output hold from address change t oh 5ns write cycle time t wc 65 ns page mode write cycle time t pwc 25 20000 ns page mode ce precharge t cp 10 ns chip enable to end of write t cw 55 ns address valid to end of write t aw 55 ns byte select to end of write t lbw , t ubw 55 ns write pulse width t wp 50 20000 ns write precharge time t weh 7.5 ns address setup time t as 0ns write recovery time t wr 0ns write to high-z output t whz 5ns data to write time overlap t dw 25 ns page mode data to write time overlap t pdw 20 ns data hold from write time t dh 0ns page mode data hold from write time t pdh 0ns end write to low-z output t ow 5ns maximum page mode cycle t pgmax 20000 ns
80 am49lv128bm june 17, 2004 timing of read cycle (ce# = oe# = v il , we# = v ih )
june 17, 2004 am49lv128bm 81 timing waveform of read cycle (we#=v ih ) a ddress ce# oe# lb#,ub# data out
82 am49lv128bm june 17, 2004 timing waveform of page mode read cycle (we# = v ih )
june 17, 2004 am49lv128bm 83 timing waveform of write cycle (we# control)
84 am49lv128bm june 17, 2004 timing waveform of write cycle (ce# control)
june 17, 2004 am49lv128bm 85 timing waveform for successive we# write cycles
86 am49lv128bm june 17, 2004 timing waveform of page mode write cycle power savings modes the psram has three power savings modes: ? reduced memory size ? partial array refresh ? deep sleep mode the operation of the power saving modes is controlled by setting the variable address register (var). this var is used to enable/disable the various low power modes. the var is set by using the timings. the register must be set in less then 1s after zz# is enabled low. reduced memory size (rms) in this mode of operation, the 32mb psram can be operated as a 8mb, 16mb or a 24mb device. the mode and array size are determined by the settings in the va register. the va regist er is set according to the timings and the bit settings . the rms mode is enabled at the time of zz# transitioning high and the mode re- mains active until the register is updated. to return to the full 32mb address space, the va register must be reset using the previously defined procedures. partial array refresh (par) in this mode, the internal refresh operation can be re- stricted to a 8mb, 16mb or 24mb portion of the array. the mode and array partition to be refreshed are de- termined by the settings in the var register. the var register is set according to the timings and the bit set- tings. in this mode, when zz# is taken low, only the portion of the array that is set in the register is re- freshed. the operating mode is only available during standby time and once zz# is returned high, the de- vice resumes full array refresh. all future par cycles will use the contents of the va register. to change the address space of the par mode, the va register must be reset using the previously defined procedures. the default state for the zz# register will be such that zz# low will put the device into par mode after 1s and never initiate a deep sleep mode unless appropri-
june 17, 2004 am49lv128bm 87 ate register is updated. this device is referred to as deep sleep inactive, or dsi device. in either device, once the sram enters deep sleep mode, the var contents are destroyed and the default register set- tings are reset. deep sleep mode in this mode of operation, the internal refresh is turned off and all data integrity of the array is lost. deep sleep is entered by bringing zz# low. after 1 s, if the var register corresponding to a4 is not set to deep sleep disabled, the device will enter deep sleep mode. the device will remain in this mode as long as zz# re- mains low.
88 am49lv128bm june 17, 2004 variable address register
june 17, 2004 am49lv128bm 89 variable address register (var) update timings
90 am49lv128bm june 17, 2004 deep sleep mode - entry/exit timings var update and deep sleep timings item symbol min max unit par and rms zz# low to we# low t zzwe 1000 ns chip (ce#, ub#/lb#) deselect to zz# low t cdzz 0ns deep sleep mode t zzmin 10 ns deep sleep recovery t r 200 ns
june 17, 2004 am49lv128bm 91 address patterns for par (a3 = 0, a4 = 1) a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 000000h - 07ffffh 512kb x 16 8mb 0 1 0 one-half of die 000000h - 0fffffh 1mb x 16 16mb x 0 0 full die 000000h-1fffffh 2mbx16 32mb 1 1 1 one-quarter of die 180000h - 1fffffh 512kb x 16 8mb 1 1 0 one-half of die 100000h - 1fffffh 1mb x 16 16mb
92 am49lv128bm june 17, 2004 address patterns for rms (a3 = 1, a4 = 1) a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 000000h - 07ffffh 512kb x 16 8mb 0 1 0 one-half of die 000000h - 0fffffh 1mb x 16 16mb x 0 0 full die 000000h - 1fffffh 2mb x 16 32mb 1 1 1 one-quarter of die 180000h - 1fffffh 512kb x 16 8mb 1 1 0 one-half of die 100000h - 1fffffh 1mb x 16 16mb
june 17, 2004 am49lv128bm 93 low power icc characteristics for psram item symbol test array partition typ max unit par mode standby current i par v in = v cc or 0v, chip disabled, t a = 85c 1/4 array 50 75 a 1/2 array 70 90 rms mode standby current i rmssb v in = v cc or 0v, chip disabled, t a = 85c 8mb device 50 75 a 16mb device 70 90 deep sleep current i zz vin = vcc or 0v, chip in zz# mode, t a = 85c 710a
94 am49lv128bm june 17, 2004 physical dimensions tld064?64-ball fine-pitch ball grid array 3309 \ 16-038.22 a package tld 064 jedec n/a d x e 12.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.10 --- --- ball height a2 0.81 --- 0.97 body thickness d 12.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 64 ball count b 0.35 --- 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b2,b3,b4,b7,b8,b9,b10 c1,c2,c9,c10,d1,d10,e1,e10 f1,f5,f6,f10,g1,g5,g6,g10 h1,h10,j1,j10,k1,k2,k9,k10 l1,l2,l3,l4,l7,l8,l9,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in th e outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 64x a1 a2 a 0.15 c a b c m m 0.08 pin a1 ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view
june 17, 2004 am49lv128bm 95 revision summary revision a (january 22, 2004) initial release. revision a+1 (january 29, 2004) connection diagrams corrected signal designation on ball h8. ac characteristics (flash) read-only operations: added figure 14. psram ac characteristics figure 32, write timing #1 (basic timing): renamed t wrc to t ah ; extended t wr to where we# returns low; extended t br to where lb#, ub# goes low. figure 33, write timing #2 (we# control): the period along we# formerly labeled t wr is now t ah . a new t wr period has been added which extends from we# going high after the first t wp period to where the sec- ond t wp period begins. figure 34, write timing #3-1 (we#/lb#/ub# byte write control): t wr has been extended to where we# returns low. figure 35, write timing #3-2 (we#/lb#/ub# byte write control): t wr has been extended to where we# returns low. write operations table: changed minimum specifica- tion for t wr from 12 to 7.5 ns. added t ah specification. revision a+2 (february 16, 2004) psram features feature list was corrected to four main features lookahead pinout diagram figure was removed and replaced by tbd. ordering information added and option that designates standard or second supplier for psram. am49lv128bm mcp with second supplier section added. revision a+3 (february 25, 2004) operating ranges removed v io from the list of supply voltages. am49lvxxxbm mcp with second supplier psram block diagram added a note clarifying zz#. revision a+4 (march 4, 2004) lookahead diagram added the lookahead diagram. revision a+5 (march 15, 2004) global changed dq designations to 0-7 and 8-15. global removed references to the 4m partial power down mode and added references to deep sleep. recommended operating conditions corrected min. and max values for v ih parameter. psram ac characteristics write operation changed column head to value, added t whol param- eter, changed min value of t bwo to 30, and added notes 8, 9, and 10. ac characteristics added power down parameters and other timing pa- rameters tables. am49lv128bm mcp with second psram supplier removed capacitance section. partial array refresh (par) removed reference to two versions. revision a6 (june 17, 2004) ?absolute maximum ratings? on page 37 changed ?voltage on vcc supply relative to vss - rating? to -0.2 to 3.6. changed ?power dissipation - rating? to 1. changed ?operating temperature - rating? to -25 to +85. ?low power icc characteristics for psram? on page 93 changed ?par mode standby current? - type to ?50? and max to ?75?. changed ?rms mode standby current - 8mb device? - type to ?50? and max to ?75?. changed ?rms mode standby current - 16mb de- vice? - type to ?70? and max to ?90?. changed ?deep sleep current? -type to ?7?. ?address patterns for rms (a3 = 1, a4 = 1)? on page 92 deleted ?three-quarters of die from table.
96 am49lv128bm june 17, 2004 deleted ?full die? from table. ?address patterns for par (a3 = 0, a4 = 1)? on page 91 added ?full die? to table. ?timing? on page 79 changed ?chip disable to high-z output - max? to 5. changed ?output disable to high-z output - max? to 5. changed ?byte select disable to high-z output - max? to 5. changed ?write to high-z output - max? to 5. ?operating characteristi cs (over specified temperature range)? on page 77 changed ?supply voltage for i/o - min? to 7.7. changed ?input high voltage - min? to 0.8. changed ?output high voltage - max? to 0.2. changed ?output low voltage - test condition? to...=0.5ma.hanged ?output low voltage - max.? to 0.2vccq. changed ?input leakage current - min.? to -1. changed ?input leakage current - max.? to 1. changed ?output leakage current - min.? to -1 changed ?output leakage current - max.? to 1. changed ?read/write operating supply current @1...-test condition? to vcc=3.1v... changed ?read/write operating supply current @65...-test condition? to vcc=3.1v... changed ?page mode operating supply current. - test condition? to vcc=3.1v... changed ?page mode operating supply current. - max.? to 25.0 changed ?maximum standby current - test condition? to vcc=3.1v... changed ?maximum standby current - max.? to 120. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limita- tion, ordinary industrial use, general offi ce use, personal use, and household use, but are not designed, developed and manufac tured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a seri ous effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolerable ( i.e., submersibl e repeater and artificial satellite). please note that fasl wi ll not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semicondu ctor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating condi- tions. if any products described in this document represent goods or technologies subject to certain restrictions on export und er the foreign ex- change and foreign trade law of japan, the us export administration regulations or the applicable laws of any other country, th e prior authorization by the respective government entity will be required for export of those products. trademarks copyright ? 2003?2004 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are regist ered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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